Digital logical sequence controller

ABSTRACT

A sequence controller of the digital logical circuit type, comprising a sequence program part and a processing circuit, wherein the desired sequence instruction is read from the sequence program part, and the sequence is processed and controlled by the processing circuit. A certain definite level is set at a branch point in an equivalent sequential circuit according to the path along which a signal of the sequential circuit is transmitted. This level and the on-off state of the branch point are stored in a memory. The given data are processed and controlled through the sequence program part and the memory.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to sequence controllers of the digitallogical circuit type, in which the desired sequence instruction is readfrom its sequence program part, and the sequence is processed andcontrolled in its processing circuit.

2. Description of the Prior Art

Being indispensable in the present-day industrialized society, thesequence control technique is widely used in the field of industrialprocess control, such as power plant and substation control, conveyorsystem control, machine tool control, assembly line control in theautomotive plant, and rolling line control. For these controls, thecontact relay sequence control has long been used. This type of sequencecontrol, however, is inconvenient for applications where designmodifications are often made on a control system, resulting indegradation of reliability. Recently, the controlled objectives havebecome much more sophisticated which has necessitated the use of anincreasing number of relays, with the result that the logical design hasbecome intricate and the approach to higher speed control has becomemore difficult.

One solution to this problem in the prior art is the sequence controllerwith computer-like control functions adapted to sequence controls, inwhich a program (i.e., a pattern of sequence control operation) isstored in a core memory by way of the keyboard according to apredetermined specific format, the process state is sampled at certaintime intervals and compared with the stored data, and an output isgenerated according to the result.

This sequence controller operates in general on flow-chart system orBoolean algebraic system (conversion system) through programming. When arelay sequence is programmed for a computer, the necessary logicaloperation is expressed in terms of Boolean algebra, which is programmedand stored in a core memory of the sequence controller. This Booleanalgebraic system offers high processing efficiency.

This programming control will be described by way of example withreference to FIGS. 1 through 3. A sequence diagram as shown in FIG. 1may be expressed by Boolean algebraic equations as follows.

    Y.sub.1 = (X.sub.1 +  X.sub.3).sup.. X.sub.2 =  X.sub.1 .sup.. X.sub.2 + X.sub.3 .sup.. X.sub.2                                    ( 1)

    y.sub.2 =  x.sub.4 .sup.. x.sub.5 + x.sub.6                ( 2)

where X₁ to X₆ stand for input contacts, among which X.sub., X₃, X₄ andX₅ are make-contacts which close the individual circuits when the coilis excited, and X₂ and X₆ are break-contacts which open the individualcircuits when the coil is excited; and Y₁ and Y₂ denote output relays.

FIG. 2 is a block diagram showing a conventional digital logical circuittype sequence controller with functions equivalent to those of theabove-mentioned relay sequence circuit. In FIG. 2, X₁, X₂, X₃, . . .denote contacts of external inputs, and the numeral 1 represents aninput selection circuit which selects the necessary input contact andsupplies datum of the state of the selected input contact to a logicalprocessing circuit 2 which is capable of performing a given sequenceprocessing. The numeral 3 denotes an output control circuit which holdsthe specific output relays Y₁ and Y₂ in on or off state according to theprocessed result reached by the processing circuit 2. The numeral 4represents a sequence program storage circuit which stores sequenceprograms and reads them in sequence and supplies the read program to theprocessing circuit 2. An example of this processing circuit isillustrated in block form in FIG. 3, in which FF₁, FF₂ and FF₃ denoteflip-flop circuits, AND a logical AND circuit, OR a logical OR circuit,and G₁ to G₅ gates. This circuit performs processing as summarized belowin reference to Y₁ as in Eq. (1).

    Memory Address                                                                           Sequence Instruction                                                                        Processing                                           ______________________________________                                        1          LOAD X.sub.1  1 X.sub.1 →FF.sub.1                                                    2 FF.sub.1 →FF.sub.2                                                   3 O→FF.sub.3                                  2          AND X.sub.2   1 X.sub.2 →FF.sub.1                                                    2 FF.sub.1. FF.sub.2 →FF.sub.2                3          OR X.sub.3    1 X.sub.3 →FF.sub.1                                                    2 FF.sub.2 + FF.sub.3 →FF.sub.3                                        3 FF.sub.1 →FF.sub.2                          4          AND X.sub.2   1 X.sub.2 →FF.sub.1                                                    2 FF.sub.1. FF.sub.2 →FF.sub.2                5          SET Y.sub.1   2 FF.sub.2 + FF.sub.3 →FF.sub.3                                        3 FF.sub.3 →OUT Y.sub.1                       ______________________________________                                         (Note: The numerals  1 , 2 , and  3 indicate the timing sequence for the      processing.)                                                             

When a sequence instruction LOAD X₁ at memory address 1 is read from amemory in the sequence program storage circuit 4, this instruction isdecoded and the state of input contact X₁ is stored in the flip-flopFF₁. Then the gates G₁ and G₃ are opened whereby the data in theflip-flop FF₁ is transferred to the flip-flop FF₂, and the binary code"0" is stored as an initial set signal in the flip-flop FF₃. Then, whenanother sequence instruction AND X₂ at address 2 is read from a memoryin the sequence program storage circuit 4, the state of complement X₂ ofinput contact X₂ is stored in the flip-flop FF₁, and the gate G₂ isopened whereby the flip-flops FF₁ and FF₂ undergo AND logic and theresult is stored in the flip-flop FF₂. The state of input contact X₃ isstored in the flip-flop FF₁ by another sequence instruction OR X₃. Thenthe gate G₄ is opened whereby the flip-flops FF₂ and FF₃ undergo ORlogic, and the result is transferred to the flip-flop FF₃. After thisstep, the gate G₁ is opened whereby the datum stored in the flip-flopFF₁ is transferred to the flip-flop FF₂. When an instruction AND X₂ ataddress 4 is read, the same processing as performed by the instructionat address 2 is carried out. Then, when an instruction SET Y₁ at address5 comes in, the gate G₄ is opened whereby the flip-flops FF₂ and FF₃undergo OR logic, and the result is transferred to the flip-flop FF₃.After this step, the gate G₅ is opened to allow the datum in theflip-flop FF₃ to be delivered to the output relay Y₁ through the outputcontrol circuit 3.

Thus, the Boolean algebraic equation, X₁ .sup.. X₂ + X₃ .sup.. X₂ = Y₁,is executed by the sequence instructions at addresses 1 to 5. In thesame manner, Boolean algebraic equations expressed by polynomials of ANDand OR can be converted into sequence instructions one after another.The sequence instructions are read one after another from the memory ofthe sequence program storage circuit 4 and executed repeatedly at highspeed. Hence the sequence controller shown in FIG. 2 performs functionsequivalent to those of the relay sequence shown in FIG. 1. When therelay sequence forms a loop as shown in FIG. 4, this sequence may beexpressed in Boolean algebra as follows.

    Y.sub.1 = X.sub.1 .sup.. X.sub.2 + X.sub.4 .sup.. X.sub.3 .sup.. X.sub.2 + X.sub.4 .sup.. X.sub.5 X.sub.6 + X.sub.1 .sup.. X.sub.3 .sup.. X.sub.5 .sup.. X.sub.6                                            ( 3)

    y.sub.2 = x.sub.4 .sup.. x.sub.5 + x.sub.1 .sup.. x.sub.3 .sup.. x.sub.5 + x.sub.1 .sup.. x.sub.2 .sup.. x.sub.6 + x.sub.4 .sup.. x.sub.3 .sup.. x.sub.2 .sup.. x.sub.6                                    ( 4)

because all the loops are to be considered, these Boolean equations areinevitably complicated. If the relay sequence comprises intricate loops,it will become extremely difficult to convert all the logical paths intoBoolean equations, and a considerable amount of effort must be made tobuild a complete sequence program.

SUMMARY OF THE INVENTION

An object of the invention is to provide an improved sequence controllerfree of the prior art drawbacks.

Another object of the invention is to provide a sequence controller withwhich a sequence program can readily be constructed.

Still another object of the present invention is to provide a sequencecontroller which is readily adaptable to a variety of sequence controlapplications.

A further object of the invention is to provide a sequence controllerwhich meets the above objects yet is low in cost.

Other objects will appear hereinafter.

These and other objects are achieved in accordance with the presentinvention which utilizes a sequence controller of the digital logicalcircuit type capable of operation in which a necessary sequenceinstruction is read from the sequence program storage and the sequenceis processed by the processing circuit; and which includes a certaindefinite level set at a branch point in an equivalent sequence circuitaccording to the path along which the signal of the sequence circuit istransmitted. This level and the on-off state of the branch point arestored in a memory, and given data are processed through the sequenceprogram storage and the memory.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing an example of a relay sequence,

FIG. 2 is a block diagram showing an example of a conventional sequencecontroller,

FIG. 3 is a block diagram of a processing circuit used with the sequencecontroller shown in FIG. 2,

FIG. 4 is a diagram showing an example of a relay sequence comprisingcomplicated loops,

FIG. 5 is a block diagram showing a sequence controller according to theinvention, and

FIG. 6 is a block diagram showing a processing circuit used with thesequence controller shown in FIG. 5.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

One embodiment of the invention will be described by referring to FIG.5. Like constituent elements are indicated by the indentical symbols inFIGS. 2 and 5. In FIG. 5, the numeral 5 denotes a memory which storesthe on-off state of a branch relay point i.e., a branch point where aninput contact is connected to another input contact or to an outputrelay contact on a sequence diagram, and which also stores a levelcorresponding to the number of relay points through which a signalpasses so as to turn on one relay point. FIG. 6 shows in block form aprocessing circuit 2 as in FIG. 5. Like constituent elements areindicated by the identical references in FIGS. 3 and 6. In FIG. 6, LR₁,LR₂ and LR₃ denote level registers indicating levels at the relaypoints, COMP₁ denotes a comparator which compares two levels with eachother and generates an output of the larger level, COMP₂ denotes acomparator which compares two levels with each other and generates anoutput of the smaller level, COMP₃ denotes a comparator and adder whichcompares two levels with each other and generates an output of thesmaller level plus 1, and Ga to Ge denote gates of level data. Thesymbol MAX represents the maximum number of levels which can be storedin the level register LR₃.

The operation of this sequence controller will be described below byreferring to the sequence diagram shown in FIG. 4. The relay sequencemay be expressed in terms of Boolean algebra as follows.

    P.sub.1 = X.sub.1 + X.sub.3 .sup.. P.sub.3 + X.sub.2 .sup.. P.sub.2 (5)

    p.sub.2 = x.sub.2 .sup.. p.sub.1 + x.sub.6 .sup.. p.sub.4  (6)

    p.sub.3 = x.sub.4 + x.sub.3 .sup.. p.sub.1 + x.sub.5 .sup.. p.sub.4 (7)

    p.sub.4 = x.sub.5 .sup.. p.sub.3 + x.sub.6 .sup.. p.sub.2  (8)

    y.sub.1 = p.sub.2                                          (9)

    y.sub.2 = p.sub.4                                          (10)

where P₁, P₂, P₃ and P₄ represent relay points (branch points) at whichinput contacts X₁ to X₆ and/or relay contacts Y₁ and Y₂ are connected toeach other.

The on-off states of the relay points P₁ to P₄ are stored in a memory 5whereby these relay points may be regarded to be equivalent to the inputcontacts. Then, assume that the input contact X₁ turns on whereby therelay point P₁ turns on, and the input contact X₃ turns on whereby therelay point P₃ turns on, and then X₁ turns off. Theoretically, underthis condition, the relay point P₁ assumes on-state depending on thecondition of X₃ P₃, and the relay point P₃ remains in on-state dependingon the condition of X₃ P₁, as opposed to the practically desiredcondition where both P₁ and P₃ are in off-state. This makes itimpossible to indicate any off-state on a practical relay sequencediagram. To solve this problem, levels are set at the individual relaypoints P₁ through P₄, so that one level is higher by 1 than another as asignal proceeds from one relay point to another. By so setting thelevels, a relay point where the level is low cannot be turned on from arelay point where the level is high. By this arrangement, the inputcontact X₁ turns on whereby the relay point P₁ turns on (level 1), andthe input contact X₃ turns on whereby the relay point P₃ turns on (level2). After this step, when the input contact X₁ turns off, the relaypoint P₁ (level 1) turns off since the condition of X₃ P₃ is level 2.Accordingly, the relay point P₃ turns off. Thus the on and off statescorrespond to the actual sequence diagram. (Note: The input contacts X₁,X₂, . . . always stand at level 0.)

To illustrate the invention, the operations of this relay sequence aresummarized below in terms of Boolean algebra, Eq. (5), P₁ = X₁ + X₃.sup.. P₃ + X₂ .sup.. P₂.

    __________________________________________________________________________    Memory                                                                             Sequence                                                                 Address                                                                            Instruction           Processing                                         __________________________________________________________________________    1    LOAD X.sub.1                                                                         1 X.sub.1 →FF.sub.1                                                                1  L(X.sub.1) →LR.sub.1                                    2 FF.sub.1 →FF.sub.2                                                               2  LR.sub.1 →LR.sub.2                                      3 0→FF.sub.3                                                                       3  MAX→LR.sub.3                                2    OR X.sub.3                                                                           1 X.sub.3 →FF.sub.1                                                                1  L(X.sub.3)→LR.sub.1                                     2 FF.sub.2 +FF.sub.3 →FF.sub.3                                                     2  LR.sub.2 →LR.sub.3 only when                                           FF.sub.2 = 1 and LR.sub.2 < LR.sub.3                           3 FF.sub.1 →FF.sub.2                                                               3  LR.sub.1 →LR.sub.2                          3    AND P.sub.3                                                                          1 P.sub.3 →FF.sub.1                                                                1  L(P.sub.3)→LR.sub.1                                     2 FF.sub.1.FF.sub.2 →FF.sub.2                                                      2  LR.sub.1 →LR.sub.2 when                                                LR.sub.1 > LR.sub.2                                4    OR X.sub.2                                                                           1 X.sub.2 →FF.sub.1                                                                1  L(X.sub.2)→LR.sub.1                                     2 FF.sub.2 + FF.sub.3 →FF.sub.3                                                    2  LR.sub.2 →LR.sub.3 only when                                           FF.sub.2 = 1 and LR.sub.2 < LR.sub.3                           3 FF.sub.1 →FF.sub.2                                                               3  LR.sub.1 →LR.sub.2                          5    AND P.sub.2                                                                          1 P.sub.2 →FF.sub.1                                                                1  L(P.sub.2)→LR.sub.1                                     2 FF.sub.1 .FF.sub.2 →FF.sub.2                                                     2  LR.sub.1 →LR.sub.2 when                                                LR.sub.1 > LR.sub.2                                6    SET P.sub.1                                                                          1 FF.sub.2 + FF.sub.3 →FF.sub.3                                                    1  LR.sub.2 →LR.sub.3 only when                                           FF.sub.2 = 1 and LR.sub.2 < LR.sub.3               2 FF.sub.3 →OUT P.sub.1                                                                        2  LR.sub.3 + 1→L(P.sub.1) when                when L(P.sub.1) ≧ LR.sub.3                                                                        L(P.sub.1) ≧ LR.sub.3                       0→OUT P.sub.1       MAX→L(P.sub.1) when                         when L(P.sub.1) < LR.sub.3 L(P.sub.1) < LR.sub.3                              __________________________________________________________________________     (Note: The numerals  1 , 2 , and  3 indicate the timing sequence for the      processing, and X.sub.1, X.sub.2, .....always stand at level 0.)         

When a sequence instruction LOAD X₁ at address 1 is read from a memoryin the sequence program part 4, this instruction is decoded, and thestate of input contact X₁ is stored in the flip-flop FF₁. Then the gateG₁ is opened whereby the data in the flip-flop FF₁ is transferred to theflip-flop FF₂, and the binary code 0 is stored as an initial set in theflip-flop FF₃. On the other hand, the level 0 of the contact X₁ isregistered in the level register LR₁, and the gate Ga is opened wherebythe data in the level register LR₁ is transferred to the level registerLR₂. The level register LR₃ is initially set to a maximum value MAX.Then, when another sequence instruction OR X₃ at address 2 is read fromthe memory in the sequence program part 4, the state of input contact X₃is stored in the flip-flop FF₁, the gate G₄ is opened, and a logic ORcombination of flip-flops FF₂ and FF₃ by OR circuit OR is stored in theflip-flop FF₃. Then the gate G₁ is opened whereby the data in theflip-flop FF₁ is transferred to the flip-flop FF₂. The level 0 of inputcontact X₃ is stored in the level register LR₁. The gate Gd opens onlywhen the flip-flop FF₂ is on (i.e., X₁ is on). If the level of the levelregister LR₂ is smaller than that of the level register LR₃, thecomparator COMP₂ generates an output of data in the level register LR₂,which is stored in the level register LR₃. Then the gate Ga is openedwhereby the data in the level register LR₁ is transferred to the levelregister LR₂. After this step, another sequence instruction AND P₃ ataddress 3 is given whereby the state of relay point P₃ is read from thememory 5. This data is stored in the flip-flop FF₁. Then the gate G₂ isopened whereby a logic AND combination of flip-flops FF₁ and FF₂ by ANDcircuit is stored in the flip-flop FF₂. The level of relay point P₃which is stored in the memory 5 is registered in the level register LR₁.When the level of the level register LR₁ is larger than that of thelevel register LR₂, the comparator COMP₁ generates an output of data inthe level register LR₁, which is stored in the level register LR₂through the gate Gb. Then, by another sequence instruction OR X₂ ataddress 4, the state of input contact X₂ is stored in the flip-flop FF₁.The gate G₄ is opened and an OR logic combination of flip-flops FF₁ andFF₃ by OR circuit is stored in the flip-flop FF₃. After this step, thegate G₁ is opened whereby the data in the flip-flop FF₁ is transferredto the flip-flop FF₂. On the other hand, the level 0 of input contact X₂is registered in the level register LR₁. When the flip-flop FF₂ is on(i.e., both P₃ and X₃ are on), the gate Gd opens. Thus, if the level ofthe level register LR₂ is smaller than that of the level register LR₃,the comparator COMP₂ generates an output of data in the level registerLR₂, which is stored in the level register LR₃. Then the gate Ga isopened whereby the data in the level register LR₁ is transferred to thelevel register LR₂. Next, by another sequence instruction AND P₂ ataddress 5, the state of the relay point P₂ is read from the memory 5,which is stored in the flip-flop FF₁. The gate G₂ is opened and alogical AND combination of flip-flops FF₁ and FF₂ by AND circuit isstored in the flip-flop FF₂. While the level of the relay point P₂ whichis stored in the memory 5 is read and registered in the level registerLR₁, the gate Gb is opened and if the level of the level register LR₁ islarger than that of the level register LR₂, the data in the levelregister LR₁ is transferred to the level register LR₂. Then by anothersequence instruction SET P₁ at address 6, the gate G₄ opens and alogical OR combination of flip-flops FF₂ and FF₃ by OR circuit istransferred to the flip-flops FF₃. On the other hand, the gate Gd isopened only when the flip-flop FF₂ is on (i.e., both P₂ and X₂ are on).If the level of the level register LR₂ is smaller than that of the levelregister LR₃, the comparator COMP₂ generates an output of data in thelevel register LR₂, which is stored in the level register LR₃. Then thelevel of the relay point P₁ is read from the memory 5. This level iscompared with the level of the level register LR₃ by the comparatorCOMP₃. When the level of the relay point P₁ is larger than or equal tothat of the level register LR₃, the gate G₅ is opened whereby the datain the flip-flop FF₃ is stored in the memory 5. When the level of therelay point P₁ is smaller than that of the level register LR₃, thebinary code 0 is stored in the P₁ memory part. Then the level of therelay point P₁ is read from the memory 5. This level is compared withthe level of the level register LR₃ by the comparator COMP₃. When thelevel of the relay point P₁ is larger than or equal to that of the levelregister LR₃, the gate Ge is opened, and 1 is added to the data in thelevel register LR₃. The result of data is stored in the P₁ memory partof the memory 5. When the level of the relay point P₁ is smaller thanthat of the level register LR₃, the P₁ memory part of the memory 5 isset to a maximum level value MAX. In the above manner, the Booleanalgebraic equation, P₁ = X₁ + X₃ .sup.. P₃ + X₂ .sup.. P₂, is executedby the sequence instructions at addresses 1 to 6.

The operation of the relay sequence will further be described in termsof Boolean Eq. (6), P₂ = X₂ .sup.. P₁ + X₆ .sup.. P₄ as summarizedbelow.

    __________________________________________________________________________    Memory                                                                             Sequence                                                                 Address                                                                            Instruction        Processing                                            __________________________________________________________________________    7    LOAD X.sub.2                                                                         1  X.sub.2 →FF.sub.1                                                               1 L(X.sub.2)→LR.sub.1                                      2  FF.sub.1 →FF.sub.2                                                              2 LR.sub.1 →LR.sub.2                                       3  0→FF.sub.3                                                                      3 MAX→LR.sub.3                                 8    AND P.sub.1                                                                          1  P.sub.1 →FF.sub.1                                                               1 L(P.sub.1)→LR.sub.1                                      2  FF.sub.1.FF.sub.2 →FF.sub.2                                                     2 LR.sub.1 →LR.sub.2 when                                                LR.sub.1 > LR.sub.2                                 9    OR X.sub.6                                                                           1  X.sub.6 →FF.sub.1                                                               1 L(X.sub.6)→LR.sub.1                                      2  FF.sub.2 + FF.sub.3 →FF.sub.3                                                   2 LR.sub.2 →LR.sub.3 only when                                           FF.sub.2 = 1, and LR.sub.2 < LR.sub.3                           3  FF.sub.1 →FF.sub.2                                                              3 LR.sub.1 →LR.sub.2                           10   AND P.sub.4                                                                          1  P.sub.4 →FF.sub.1                                                               1 L(P.sub.4)→LR.sub.1                                      2  FF.sub.1 .FF.sub.2 →FF.sub.2                                                    2 LR.sub.1 →LR.sub. 2 when                                               LR.sub.1 > LR.sub.2                                 11   SET P.sub.2                                                                          1  FF.sub.2 + FF.sub.3 →FF.sub.3                                                   1 LR.sub.2 →LR.sub.3 only when                                           FF.sub.2 = 1 and LR.sub.2 < LR.sub.3                            2  FF.sub.3 →OUT P.sub.2                                                           2 LR.sub.3 + 1→L(P.sub.2) when                             when L(P.sub.2) ≧ LR.sub.3                                                            L(P.sub.2) ≧ LR.sub.3                                   0→OUT P.sub.2                                                                         MAX→L(P.sub.2) when                                     when L(P.sub.2) < LR.sub.3                                                                   L(P.sub.2) < LR.sub.3                              __________________________________________________________________________

More specifically, when a sequence instruction LOAD X₂ at address 7 isread from a memory in the sequence program part 4, this instruction isdecoded and the state of input contact X₂ is stored in the flip-flopFF₁. Then the gate G₁ is opened whereby the data in the flip-flop FF₁ isstored in the flip-flop FF₂, and the binary code 0 is stored in theflip-flop FF₃. On the other hand, the level 0 of the contact X₂ isregistered in the level register LR₁. When the gate Ga opens, the datain the level register LR₁ is transferred to the level register LR₂. Thelevel register LR₃ is set to a maximum level value. Then, by anothersequence instruction AND P₁ at address 8, the state of the relay pointP₁ is read from the memory 5 and stored in the flip-flop FF₁. The gateG₂ opens and a logical AND combination of flip-flops FF₁ and FF₂ by ANDcircuit is stored in the flip-flop FF₂. The level of the relay point P₁which is stored in the memory 5 is registered in the level register LR₁.When the level of the level register LR₁ is larger than that of thelevel register LR₂, the comparator COMP₁ generates an output of data inthe level register LR₁. Then the gate Gb is opened and this data isstored in the level register LR₂. After this set, the state of inputcontact X₆ is stored in the flip-flop FF₁ by another sequenceinstruction OR X₆ at address 9. Then the gate G₄ is opened and a logicalOR combination of flip-flops FF₂ and FF₃ by OR circuit is stored in theflip-flop FF₃. The gate G₁ is opened whereby the data in the flip-flopFF₁ is transferred to the flip-flop FF₂. The level 0 of the inputcontact X₆ is stored in the level register LR₁. The gate Ga opens onlywhen the flip-flop FF₂ is on. If the level of the level register LR₂ issmaller than that of the level register LR₃, the comparator COMP₂generates an output of data in the level register LR₂, which istransferred to the level register LR₃. Then the gate Ga is opened andthe data in the level register LR₁ is transferred to the level registerLR₂.

After this step, the state of the relay point P₄ is read from the memory5 by another sequence instruction AND P₄ at address 10. This data isstored in the flip-flop FF₁. Then the gate G₂ is opened and a logicalAND combination of flip-flops FF₁ and FF₂ by AND circuit is stored inthe flip-flop FF₂. The level of the relay point P₄ which is stored inthe memory 5 is read and stored in the level register LR₁. The gate Gbis thereby opened, and when the level of the level register LR₁ islarger than that of the level register LR₂, the data in the levelregister LR₁ is transferred to the level register LR₂.

The gate G₄ is opened by another sequence instruction SET P₂ at address11, and a logical OR combination of flip-flops FF₂ and FF₃ by OR circuitis transferred to the flip-flop FF₃. The gate Gd is opened only when theflip-flop FF₂ is on. When the level of the level register LR₂ is smallerthan that of the level register LR₃, the comparator COMP₂ generates anoutput of data in the level register LR₂, which is stored in the levelregister LR₃. Then, this level is compared with the level of the relaypoint P₂ by the comparator COMP₃. When the level of the relay point P₂is larger than or equal to that of the level register LR₃, the gate G₅opens whereby the data in the flip-flop FF₃ is stored in the P₂ memorypart of the memory 5. When the level of the relay point P₂ is smallerthan that of the level register LR₃, the binary code 0 is stored in theP₂ memory part. When the level of the relay point P₂ is larger than orequal to that of the level register LR₃, the gate Ge opens and 1 isadded to the data in the level register LR₃. The resultant data isstored in the P₂ memory part of the memory 5. When the level of therelay point P₂ is smaller than that of the level register LR₃, the P₂memory part of the memory 5 is set to a maximum level value MAX. In theabove manner, the Boolean equation, P₂ = X₂ .sup.. P₁ + X₆ .sup.. P₄, isexecuted on the sequence instructions at addresses 7 to 11.

In the same manner as above, Boolean Eqs. (7) to (10) can be convertedrespectively into sequence programs.

Because this sequence program is executed repeatedly at high speed, thesequence controller shown in FIG. 5 performs functions equivalent tothose of the relay sequence shown in FIG. 4.

According to the invention, as has been described above, the branchpoints where input contacts and/or relay contacts on a sequence diagramare connected to each other are used as relay points. The on and offstates of these relay points and the levels corresponding to the numberof relay points by way of which one relay point is turned on are storedin a memory and a given data is processed according to the level.Accordingly, the sequence program can be set up exactly according toBoolean algebraic equations using relay points. Because these Booleanequations can be easily derived, this sequence controller can provide asequence program quickly and accurately. In other words, the sequencecontroller of this invention can readily be adapted to a wide variety ofsequence control applications.

While one preferred embodiment of the invention has been described andillustrated in detail, it is to be clearly understood that this shouldnot be construed as necessarily limiting the scope of the invention,since it is apparent that many changes can be made to the disclosedprinciples by those skilled in the art in order to suit particularapplications.

What is claimed as new and desired to be secured by Letters Patent ofthe United States is:
 1. A sequence controller comprising:an inputselection circuit; a logical processing circuit; an output controlcircuit; a sequence program storage circuit; a memory circuit; meansconnecting a plurality of input contacts to the input selection circuit;means connecting the input selection circuit to the logical processingcircuit; means connecting the logical processing circuit and the memorycircuit; means connecting the memory circuit and the logical processingcircuit to the output control circuit; means connecting the sequenceprogram storage circuit to the logical processing circuit; meansconnecting a plurality of output relays to the output control circuit tobe controlled thereby; the sequence program storage circuit storing arelay sequence having branch points; the level of each branch point andits on-off state being stored in the memory circuit; whereby data fromthe plurality of input contacts is processed in accordance with therelay sequence stored in the sequence program storage circuit to controlthe output relays.
 2. A sequence controller as claimed in claim 2wherein the logical processing circuit comprises:a logical processingpart for performing logical operations in accordance with a Booleanalgebraic equation and a level processing part for processing the levelsof the branch points.
 3. A sequence controller as claimed in claim 2wherein the logical processing part comprises:a first memory circuit fortemporarily storing input data, a second memory circuit for temporarilystoring data stored in the first memory circuit, an AND circuit forperforming AND logic on the data stored in the first and second memorycircuits and supplying the resultant data to the second memory circuit,a third memory circuit for receiving and storing an initial set signaland an OR circuit for performing OR logic on the data stored in thesecond and third memory circuits and supplying the resultant data to thethird memory circuit to be derived as an output.
 4. A sequencecontroller as claimed in claim 2 wherein the level processing partcomprises:a first level register for temporarily storing an input level,a second level register for receiving and temporarily storing the levelstored in the first level register, a first comparator for comparing thelevel of the first level register with the level of the second levelregister and supplying the larger level to the second level register, athird level register for receiving and storing an initial set signal, asecond comparator for comparing the level stored in the second levelregister with the level stored in the third level register and supplyingthe smaller level to the third level register, and a third comparatorfor comparing the level stored in the third level register with thelevel of a branch point stored in the memory means and generating anoutput signal representing the smaller level plus one.
 5. A sequencecontroller as claimed in claim 2 wherein the logical processing partcomprises:first, second, third and fourth gates, a first flip-flop fortemporarily storing input data, a second flip-flop for receiving theoutput of the first flip-flop through the first gate, an AND element forperforming AND logic on the output of the first flip-flop and the outputof the second flip-flop and supplying the resultant data to the secondflip-flop through the second gate, a third flip-flop for receiving aninitial set signal through the third gate, an OR element for performingOR logic on the output of the second flip-flop and the output of thethird flip-flop and supplying the resultant data to the third flip-flopthrough the fourth gate,and wherein the level processing part comprises:fifth, sixth, seventh and eighth gates, a first level register fortemporarily storing an input level, a second level register forreceiving the output of the first level register through the fifth gate,a first comparator for comparing the output of the first level registerwith the level of the second level register and supplying the largerlevel to the second level register through the sixth gate, a third levelregister for receiving an initial set signal through the seventh gate, asecond comparator for comparing the output of the second level registerwith the output of the third level register and supplying the smallerlevel to the third level register through the eighth gate, a thirdcomparator for comparing the output of the third level register with theoutput of a branch point level stored in the memory circuit andgenerating an output signal representing the smaller level plus onewhereby the output of the third flip-flop of the logical processing partand the output of the third comparator of the level processing part arestored in the memory circuit.